I'm new to verilog and please help me figure out what might be the error -

module ram_1_verilog(input ena,input enb,   input wea, input web,   input oe,   input clk);  line :25   input [7:0] addr_a;      //error line :26   input [7:0]addr_b;       //error line :27   input reg [7:0] dout1;   //error line :28   output reg [7:0] dout_2; //error  reg [7:0] ram [255:0];  @(posedge clk) begin   if(ena == 1 && wea == 1) begin  line 35  ram(addr_a) <= dout1;      //error    end end  @(posedge clk) begin   if(enb == 1 && web == 0) begin   line : 44 dout_2 <= ram(addr_b);  //error   end end endmodule 

errors:

syntax error near "<=". line 35 line 25: port addr_a not defined verilog file c:/documents , settings/verilog_examples/ram_1_verilog.v ignored due errors line 25: port declaration not allowed in ram_1_verilog formal port declaration list line 26: port addr_b not defined line 26: port addr_b not defined line 26: port declaration not allowed in ram_1_verilog formal port declaration list line 27: port dout1 not defined  line 27: non-net port dout1 cannot of mode input line 27: port declaration not allowed in ram_1_verilog formal port declaration list line 28: port dout_2 not defined line 28: port declaration not allowed in ram_1_verilog formal port declaration list line 35: dout1 not task  line 44: ram not function. line 44: ram expects 0 arguments. line 44: cannot assign unpacked type packed type. 

i'm working on dpram,it worked fine in vhdl same logic getting errors in verilog, please me figure out might error.

1. lines 35 , 44 - you've made twice same mistake, explained tim.
2. lines 25-28 flagged, because addr_a, addr_b, dout1 , dout_2 not declared in port declaration list , defined input/output.